The present invention relates generally to the testing of memory integrated circuits (IC), and, more specifically, to a method and apparatus for reducing the test time of memory cells in a dynamic random access memory (DRAM).
During the manufacture of dynamic random access memories (xe2x80x9cDRAMsxe2x80x9d), it is necessary to test the DRAM to assure that it is operating properly. Electronic systems containing DRAMs, such as computers, normally test the DRAMs when power is initially applied to the system. A DRAM is typically arranged as an array of individual memory cells. In order to assure that each memory cell is operating properly, prior art test methods write data having a first binary value (e.g., a 1) to all memory cells in the memory array. For a memory array having n rows and m columns of memory cells, it requires nxc3x97m bus cycles to write the first binary data values to all the memory cells in the memory array. A bus cycle is the period of time it takes to write or read data to or from an individual memory cell in the DRAM. After having written the first binary data values to the memory cells, this data must be read from the memory cells to assure that each memory cell is operating properly. Once again, this requires nxc3x97m bus cycles to read the data having a first binary value. Data having a second binary value (e.g., a 0) is next written to each memory cell in the memory array and is then read from each memory cell to assure each memory cell is operating properly. Each of these read and write operations also requires nxc3x97m bus cycles to complete. Therefore, to test each memory cell in the memory array, a total of four times nxc3x97m bus cycles is required. In the case of a 16 megabitxc3x974 DRAM, 67,108,864 bus cycles are required to perform a complete test of every memory cell.
To reduce the number of cycles required to test a memory array, various prior art row copy circuits have been developed which simultaneously write data to multiple memory cells. A typical prior art row copy circuit includes a memory array with multiple row access lines, multiple paired digit lines which intersect the row access lines, and a plurality of memory cells coupled at the intersections to form rows of memory cells. The row access lines provide access to associated rows of memory cells and the paired digit lines carry data to and from the accessed memory cells. A sense amplifier is coupled to each pair of digit lines for sensing the data stored by an accessed memory cell and providing that data on the digit lines. The sense amplifier provides the data on the digit lines until an equilibrate control erases the data on the multiple paired digit lines.
The row copy circuit further includes an on-chip circuit that copies data carried by the paired digit lines and stored in a first row of memory cells to at least one other row of memory cells by suspending operation of the equilibrate control to prevent erasure of the data on the paired digit lines. The row copy circuit accesses a first row of memory cells so that the sense amplifiers store the data placed on the digit lines by the accessed first row of memory cells. The row copy circuit then accesses subsequent rows of memory cells to copy the data provided by the sense amplifiers on the digit lines into the other rows of memory cells in the memory array. This circuit thus allows a test pattern of data to be more quickly written to the memory cells of the memory array via the row copy operation. The data written to the memory cells through the row copy operation must be read from the memory cells through a standard read cycle to verify that each memory cell is operating properly.
As will be appreciated by one skilled in the art, the greater the number of bus cycles required to test the memory cells in a DRAM the greater the time and the cost of testing the DRAM. Thus, it is desirable to develop a test system which reduces the number of bus cycles required to test the memory cells of a DRAM.
A circuit transfers data in an array of memory cells arranged in rows and columns. In one embodiment, the circuit comprises a plurality of row lines, a plurality of pairs of complementary digit lines, and an array of memory cells, each memory cell having a control terminal coupled to one of the row lines and a data terminal coupled to one of the complementary digit lines of one of the pairs of complementary digit lines responsive to a row enable signal on the row line of the row corresponding to the memory cell. A plurality of sense amplifiers are included in the circuit, each sense amplifier coupled to an associated pair of first and second complementary digit lines which senses a voltage differential between the first and second complementary digit lines and, in response to the sensed voltage differential, drives the first and second complementary digit lines to voltage levels corresponding to complementary logic states. A plurality of equilibration circuits are also included in the circuit, each equilibration circuit coupled between one of the pairs of complementary digit lines and operable to equalize the voltage level on each pair of complementary digit lines to a predetermined level responsive to an equilibration signal. A control circuit is coupled to the plurality of row lines and the equilibration circuits. The control circuit is operable to: write a pattern of data to an initial row of the memory array; generate the equilibrate signal; apply a row enable signal to the row line of the memory cells in the initial row; terminate the row enable signal for the initial row; apply a row enable signal to the row line to which the memory cells in another row are connected; terminate the row enable signal for the another row; and generate the equilibrate signal.